{"id":6811,"date":"2026-09-08T10:01:11","date_gmt":"2026-09-08T10:01:11","guid":{"rendered":"https:\/\/areeblog.com\/?p=6811"},"modified":"2026-09-08T10:01:11","modified_gmt":"2026-09-08T10:01:11","slug":"asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips","status":"publish","type":"post","link":"https:\/\/areeblog.com\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\/","title":{"rendered":"ASML Plans Larger EUV Masks to Help Produce Bigger AI Chips"},"content":{"rendered":"

\"ASML<\/p>\n

ASML plans to work with major chipmakers to develop larger photomasks for its High Numerical Aperture EUV lithography systems, a move aimed at allowing the technology to be used for some of the large processors being developed for AI<\/a> data centers.<\/p>\n

The Dutch semiconductor equipment maker said the industry will work toward moving from the 6-inch photomask format used today to a larger 12-inch format. The initiative is intended to address a size limitation affecting High-NA EUV systems.<\/p>\n

ASML’s announcement comes as chip designers continue to build large processors for data centers. According to Reuters<\/a>, existing EUV systems can print chips of up to about 800 square millimeters, a size that companies including Nvidia and Google are already designing toward.<\/p>\n

High-NA EUV systems can print finer features than ASML’s existing EUV machines, but their current mask size limits how large a chip can be printed. ASML plans to address that restriction by developing larger masks for the newer systems.<\/p>\n

The company expects the larger-mask technology to support chips as large as today’s biggest data-center processors while also encouraging wider use of High-NA EUV in high-volume manufacturing.<\/p>\n

High-NA EUV increases the numerical aperture of ASML’s EUV systems from 0.33 to 0.55. The company’s TWINSCAN EXE:5200B<\/a>, for example, uses 0.55-NA optics and is designed for 8-nanometer resolution.<\/p>\n

ASML says the EXE:5200B can print features 1.7 times smaller in a single exposure than its NXE systems and can achieve transistor densities 2.9 times higher. The company says the system is designed to reduce process complexity and improve wafer output in high-volume manufacturing.<\/p>\n

The challenge is that High-NA’s optical design comes with a smaller exposure field. That makes the current mask arrangement less suitable for some very large chip designs.<\/p>\n

The proposed move to larger masks is expected to reduce the need for stitching, in which different sections of a large circuit pattern are exposed and joined together.<\/p>\n

ASML Chief Technology Officer Marco Pieters told Reuters that a successful transition to the larger-mask format could increase the productivity of High-NA systems by about 40%.<\/p>\n

ASML and TSMC are targeting a pilot line using the larger masks by 2031. The companies expect the technology to be ready for high-volume production by 2033.<\/p>\n

TSMC separately said it plans to use ASML’s High-NA technology in advanced-node high-volume production from 2030. That would put the technology on a path toward broader commercial use before the larger-mask system reaches its planned high-volume production stage.<\/p>\n

Samsung has also joined the industry initiative. In a September 8 announcement<\/a>, Samsung said it would participate in the development of the 12-inch photomask platform and work with industry partners on the required mask technologies and supporting infrastructure.<\/p>\n

Samsung said the transition from 6-inch to 12-inch masks is expected to improve fab productivity, lower chipmaking costs and remove stitching constraints for future leading-edge chips.<\/p>\n

Samsung also plans to introduce ASML’s High-NA EUV technology into future DRAM high-volume manufacturing by 2028. The company described the planned deployment as the first of its kind in the industry.<\/p>\n

SK hynix is evaluating participation in the consortium covering the introduction of 12-inch masks. The company is separately targeting 2028 for applying High-NA EUV processes to DRAM mass production.<\/p>\n

High-NA EUV is already being used in production at Intel. In July, ASML said Intel Foundry had entered high-volume manufacturing for a subset of Intel Core Ultra Series 3 processors, code-named Panther Lake, using ASML’s EXE High-NA EUV technology.<\/p>\n

ASML said specific Intel 18A layers had been dual-qualified on High-NA EUV in Oregon, with products shipping to customers at yields matched to the company’s NXE platform.<\/p>\n

The development gives ASML an early production milestone for High-NA while other major chipmakers prepare their own deployments. Reuters reported that the newer systems are currently being used for production at Intel but had not yet entered high-volume work at TSMC or Samsung.<\/p>\n

ASML has positioned High-NA EUV as the next generation of its EUV platform. The company says the technology is intended to provide higher contrast and finer resolution while reducing the number of process steps required for some advanced chip layers.<\/p>\n

For AI chipmakers, the larger-mask initiative addresses a different problem. The goal is not simply to print smaller features, but to make the finer patterning capability of High-NA available for physically large processors as well.<\/p>\n

That combination could become increasingly relevant as data-center chips grow in size and complexity. For now, however, the 12-inch mask technology remains a development project, with a pilot line planned for 2031 and high-volume production targeted for 2033.<\/p>\n

ASML’s latest announcement therefore represents a longer-term effort to remove a current limitation from High-NA EUV and broaden its use in advanced logic and memory manufacturing.<\/p>\n","protected":false},"excerpt":{"rendered":"

ASML plans to work with major chipmakers to develop larger photomasks for its High Numerical Aperture EUV lithography systems, a move aimed at allowing the technology to be used for some of the large processors being developed for AI data centers. The Dutch semiconductor equipment maker said the industry will work toward moving from the […]<\/p>\n","protected":false},"author":4,"featured_media":6812,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"content-type":"","_monsterinsights_skip_tracking":false,"_jetpack_newsletter_access":"","_jetpack_dont_email_post_to_subs":false,"_jetpack_newsletter_tier_id":0,"_jetpack_memberships_contains_paywalled_content":false,"_jetpack_memberships_contains_paid_content":false,"footnotes":""},"categories":[164],"tags":[166],"class_list":["post-6811","post","type-post","status-publish","format-standard","has-post-thumbnail","category-tech-updates","tag-ai"],"share_on_mastodon":{"url":"","error":""},"yoast_head":"\nASML Plans Larger EUV Masks to Help Produce Bigger AI Chips - Aree Blog<\/title>\n<meta name=\"description\" content=\"ASML plans larger EUV masks with TSMC and Samsung to support bigger AI chips and improve High-NA production efficiency.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/areeblog.com\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"ASML Plans Larger EUV Masks to Help Produce Bigger AI Chips\" \/>\n<meta property=\"og:description\" content=\"ASML plans larger EUV masks with TSMC and Samsung to support bigger AI chips and improve High-NA production efficiency.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/areeblog.com\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\/\" \/>\n<meta property=\"og:site_name\" content=\"Aree Blog\" \/>\n<meta property=\"article:published_time\" content=\"2026-09-08T10:01:11+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/areeblog.com\/wp-content\/uploads\/2026\/09\/images-54.jpeg\" \/>\n\t<meta property=\"og:image:width\" content=\"588\" \/>\n\t<meta property=\"og:image:height\" content=\"393\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/jpeg\" \/>\n<meta name=\"author\" content=\"Samuel Ogori\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Samuel Ogori\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"4 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\\\/\\\/schema.org\",\"@graph\":[{\"@type\":\"Article\",\"@id\":\"https:\\\/\\\/areeblog.com\\\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\\\/#article\",\"isPartOf\":{\"@id\":\"https:\\\/\\\/areeblog.com\\\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\\\/\"},\"author\":{\"name\":\"Samuel Ogori\",\"@id\":\"https:\\\/\\\/areeblog.com\\\/#\\\/schema\\\/person\\\/6a78eeede4fadf1402a1c6fa18892c2a\"},\"headline\":\"ASML Plans Larger EUV Masks to Help Produce Bigger AI Chips\",\"datePublished\":\"2026-09-08T10:01:11+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\\\/\\\/areeblog.com\\\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\\\/\"},\"wordCount\":786,\"commentCount\":0,\"image\":{\"@id\":\"https:\\\/\\\/areeblog.com\\\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\\\/#primaryimage\"},\"thumbnailUrl\":\"https:\\\/\\\/areeblog.com\\\/wp-content\\\/uploads\\\/2026\\\/09\\\/images-54.jpeg\",\"keywords\":[\"AI\"],\"articleSection\":[\"Tech Updates\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\\\/\\\/areeblog.com\\\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\\\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\\\/\\\/areeblog.com\\\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\\\/\",\"url\":\"https:\\\/\\\/areeblog.com\\\/asml-plans-larger-euv-masks-to-help-produce-bigger-ai-chips\\\/\",\"name\":\"ASML Plans Larger EUV Masks to Help Produce Bigger AI Chips - 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Companies have\u2026","rel":"","context":"In "Artificial Intelligence"","block_context":{"text":"Artificial Intelligence","link":"https:\/\/areeblog.com\/category\/artificial-intelligence\/"},"img":{"alt_text":"Why Energy Is Becoming the Limiting Factor for AI","src":"https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260712-WA0027.jpg?resize=350%2C200&ssl=1","width":350,"height":200,"srcset":"https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260712-WA0027.jpg?resize=350%2C200&ssl=1 1x, https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260712-WA0027.jpg?resize=525%2C300&ssl=1 1.5x, https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260712-WA0027.jpg?resize=700%2C400&ssl=1 2x, https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260712-WA0027.jpg?resize=1050%2C600&ssl=1 3x"},"classes":[]},{"id":6285,"url":"https:\/\/areeblog.com\/why-high-bandwidth-memory-hbm-is-becoming-just-as-critical-as-gpus\/","url_meta":{"origin":6811,"position":4},"title":"Why High-Bandwidth Memory (HBM) Is Becoming Just as Critical as GPUs","author":"Daniel Chinonso John","date":"July 11, 2026","format":false,"excerpt":"What if the biggest obstacle to building faster AI systems isn't the GPU anymore? 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Yet behind\u2026","rel":"","context":"In "Artificial Intelligence"","block_context":{"text":"Artificial Intelligence","link":"https:\/\/areeblog.com\/category\/artificial-intelligence\/"},"img":{"alt_text":"Why High-Bandwidth Memory (HBM) Is Becoming Just as Critical as GPUs","src":"https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260711-WA0007.jpg?resize=350%2C200&ssl=1","width":350,"height":200,"srcset":"https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260711-WA0007.jpg?resize=350%2C200&ssl=1 1x, https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260711-WA0007.jpg?resize=525%2C300&ssl=1 1.5x, https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260711-WA0007.jpg?resize=700%2C400&ssl=1 2x, https:\/\/i0.wp.com\/areeblog.com\/wp-content\/uploads\/2026\/07\/IMG-20260711-WA0007.jpg?resize=1050%2C600&ssl=1 3x"},"classes":[]},{"id":6575,"url":"https:\/\/areeblog.com\/london-ai-infrastructure-startup-callosum-raises-100-million-seed-round-led-by-atomico\/","url_meta":{"origin":6811,"position":5},"title":"London AI Infrastructure Startup Callosum Raises $100 Million Seed Round Led by Atomico","author":"Daniel Chinonso John","date":"August 21, 2026","format":false,"excerpt":"London-based artificial intelligence infrastructure startup Callosum has raised $100 million (\u20ac85.4 million) in a seed funding round led by Atomico, as the company develops software designed to route AI workloads across different models and computing hardware. The round also includes Plural, DCVC and the UK's Sovereign AI Fund. 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